A liquid crystal display has been widely applied to products, such as laptop computers, PDAs (Personal Digital Assistants), flat-screen TVs, mobile phones or the like, due to its merits of low radiation, small volume, low power consumption and the like. A conventional liquid crystal display drives a chip on a display panel using an external driving chip to display images. However, in order to reduce the number of elements and reduce manufacturing cost, it is gradually developed to directly manufacture a driving circuit structure onto the display panel by adopting for example a GOA technique in recent years.
The GOA technique is integrating a gate driving circuit of a TFT LCD (Thin Film Transistor Liquid Crystal Display) on a glass substrate to form scan driving for a liquid crystal panel. In comparison with a traditional driving technique by using COF (Chip On Flex/Film), the GOA technique may save the manufacturing cost significantly, also omit a bonding process of COF at a side of a gate, and offer great advantages for enhancing production capacity. Thus, the GOA is a major technique of the development of the future liquid crystal panel.
As shown in FIG. 1, a GOA circuit of a current liquid crystal panel generally includes a plurality of cascade single-stage GOA circuit units, and each of the single-stage GOA circuit units corresponds to a scan driving line in a corresponding level. Each single-stage GOA circuit unit may include: a pull-up control unit {circle around (1)}, a pull-up unit {circle around (2)}, a signal downlink unit {circle around (3)}, a pull-down unit {circle around (4)}, a pull-down maintaining unit {circle around (5)}, and a bootstrap capacitance {circle around (6)}.
In FIG. 1, the pull-up control unit {circle around (1)} is mainly used for implementing pre-charging of a pre-charging node Q(N), to which a start signal ST(N−1) and a scan driving signal G(N−1) from a GOA circuit unit of an upper stage are generally input. The pull-up unit {circle around (2)} is mainly used for increasing a potential of a scan driving signal G(N) of a current level. The signal downlink unit {circle around (3)} is mainly used for controlling turning on and off signal transmission to a GOA circuit unit of a lower stage. The pull-down unit {circle around (4)} is mainly used for pulling down potentials of the pre-charging node Q(N) and the scan driving signal G(N) of the current level to a low power source voltage VSS. The pull-down maintaining unit {circle around (5)} is mainly used for maintaining the potentials of the pre-charging node Q(N) and the scan driving signal G(N) of the current level at the low power source voltage VSS unchangeable. The bootstrap capacitance {circle around (6)} is mainly used for proving and maintaining the potential of the pre-charging node Q(N), and this is helpful for the pull-up unit {circle around (2)} to output the scan driving signal G(N).
The pull-down maintaining unit {circle around (5)} actually includes an inverter. For example, the pull-down maintaining unit {circle around (5)} may be constituted by using a Darlington inverter, of which a specific circuit structure is shown in FIG. 2. The Darlington inverter may include four thin film transistors and has an input end Input and an output end Output. If a control signal LC is set to be a high potential signal always and a low power source voltage VSS is set to be a low potential signal always, the output end Output outputs the low potential signal when the input end Input inputs the high potential signal, and the output end Output outputs the high potential signal when the input end Input inputs the low potential signal. When the pull-down maintaining unit {circle around (5)} includes the Darlington inverter as shown in FIG. 2, its specific circuit structure may be illustrated in FIG. 3: taking a 2CK signal as an example, two pull-down maintaining units 1 and 2 are generally provided to work alternatively to prevent thin film transistors T32, T42, T33 and T43 from being affected by a PBS (Positive Bias Stress) for long time so that a threshold voltage Vth of a device is caused to drift positively, thereby causing a device failure of the GOA circuit.
FIG. 4 is an equivalent circuit diagram of a thin film transistor (TFT). As shown in FIG. 4, three electrodes of the TFT will be referred to as a gate electrode Gate, a source electrode Source and a drain electrode Drain, respectively, in the present disclosure. Correspondingly, voltages applied to the electrodes are marked as Vg, Vs and Vd, respectively. Here, the source electrode Source and the drain electrode Drain do not have any difference in fact. In order to facilitate explanation, in exemplary embodiments, generally, an end having the lower voltage is referred to as a source electrode Source, while the other end having the higher voltage is referred to as a drain electrode Drain. Thus, a voltage Vgs for determining an On-state of the TFT satisfies Vgs=Vg−Vs. When Vgs>0, the TFT is in the On-state, a current flows from the drain electrode Drain to the source electrode Source; and when Vgs<0, the TFT is in an Off-state. Selectively, in other exemplary embodiments, an end having the lower voltage of the TFT may also be referred to as a drain electrode Drain, while the other end having the higher voltage of the TFT is referred to as a source electrode Source, that is, when the TFT is in the On-state, the current flows from the source electrode Source to the drain electrode Drain.
Next, a technical problem to be encountered by the present disclosure will be illustrated. A waveform of the control signal LC may be set according to FIG. 5. Referring to FIG. 3 together with FIG. 5, when a first control signal LC1 is at a high potential and a second control signal LC2 is at a low potential, the pull-down maintaining unit 1 is in a working state, while the pull-down maintaining unit 2 is in a closed state. At this moment, a point A is at the high potential, the TFTs T32 and T42 are affected by the PBS; and a point B is at the low potential, the TFTs T33 and T43 are affected by an NBS (Negative Bias Stress). Similarly, when the first control signal LC1 is at the low potential and the second control signal LC2 is at the high potential, the pull-down maintaining unit 2 is in the working state, while the pull-down maintaining unit 1 is in the closed state. At this moment, the point A is at the low potential, the TFTs T32 and T42 may be affected by the NBS; and the point B is at the high potential, the TFTs T33 and T43 may be affected by the PBS. Thus, during a period of time, the TFTs T32, T42, T33 and T43 located between the point A and the point B may be affected not only by the PBS but also by the NBS such that the device failure caused due to charge trapping may be relieved to an extent.
However, as for another TFTs in FIG. 3, for example, as for four TFTs T52, T54, T62 and T64, cases are significantly different. Gate electrodes of the above four TFTs are all connected to a point Q. The point Q is a pre-charging node, which is at the high potential only when the scan lines of the upper level and the current level are turned on while is at the low potential at other times. Thus, a time duty ratio of the low and high potentials of the point Q may be estimated as about 2:(n−2), wherein n is the number of scan lines of the display panel. Accordingly, since the point Q is at the low potential for a long term, the device failure will be easily caused because the four TFT devices will be affected by the NBS for the long term.